1. Field of the Invention
The present invention relates to a semiconductor wafer used for fabricating a wafer-level chip-size package-type semiconductor device, an IC chip having bump electrodes, or the like. The present invention also relates to a semiconductor device formed from such semiconductor wafer.
2. Description of the Related Art
In a conventional semiconductor wafer which is used for a wafer-level chip-size package-type semiconductor device or for an IC chip having bump electrodes, integrated circuits are formed on a plurality of element areas on a silicon substrate. Marks for measuring the pattern formation accuracy and elements for evaluating the electric characteristics are formed in dicing areas defined between adjacent element areas. The pattern formation accuracy measurement marks are partially covered with a protective layer when the protective layer for covering the element area is formed. Thus, damage of the resist film when second interconnects (re-wiring) are formed on the protective layer is prevented. The damage would occur if air was caught in a micro-space formed on a pattern formation accuracy measurement mark. Also, the cracking to be generated in the protective layer on an element area is prevented. Specifically, when the dicing area is cut by a dicing saw using free areas at predetermined spacing created between the protective layer which covers the pattern formation accuracy measurement mark and the protective layer which covers the element area, the cracking tends to be produced, but this cracking is prevented. This semiconductor wafer is disclosed in, for example, Japanese Patent Application Kokai (Laid-Open) No. 11-191541 (page 3, paragraph 0007 to page 4, paragraph 0013, FIG. 1 and FIG. 2).
Expectations to further downsize and increase production of wafer-level chip-size package-type semiconductor devices are increasing as electronic equipment sizes decrease and sales thereof expand recently.
In order to respond to further downsizing and increase in production of semiconductor devices, it is necessary to increase the number of semiconductor devices to be fabricated from one semiconductor wafer, by decreasing the size of semiconductor devices as a result of increasing the density of the integrated circuits formed on the semiconductor wafer, and by decreasing the size of the dicing area.
In the above described prior art, the cracking to be generated in the protective layer on the element area when the dicing area is cut by the dicing saw is prevented by the free areas defined at the predetermined distance between the protective layer of the dicing area and the protective layer of the element area. Therefore, if the dicing area is decreased, then the predetermined distance cannot be taken sufficiently large. If a groove of which aspect ratio (i.e., the thickness of the protective layer divided by the above-mentioned predetermined distance, or the depth divided by the width) is 0.5 or more, in other words if the depth of the groove is more than half the width is formed, the air caught in the groove swells when the resist film is pre-baked in the subsequent step of forming second interconnects, and resist film is damaged. Accordingly, plating precipitates in an undefined form at unexpected locations, which causes appearance defects, and the plate thickness of the second interconnects disperses.
When interconnects integrate power supply wires and are formed on an active area to downsize a semiconductor device, a seal ring is often formed in the active area outside the interconnects in order to stop the cracking of the protective layer from reaching the integrated circuit. If the seal ring is located close to the interconnects due to downsizing, a groove is formed in the protective layer between the seal ring and interconnects. If the aspect ratio of this groove is 0.5 or more, then resist film is damaged when the second interconnects are formed, as described above, and plating precipitates in an undefined form at unexpected locations. This causes appearance defects, and the plate thickness of second interconnects disperses.